1. Field of the Invention
The present invention relates generally to a memory circuit structure and the semiconductor process for manufacturing the same, and more particularly, to a semiconductor process for manufacturing NAND flash circuit structure using spacer self-aligned double patterning (SADP) scheme.
2. Description of the Prior Art
The principle of a photolithographic process is to transfer a circuit pattern on a mask to a wafer by a method of exposure and development, thereby producing specific circuit patterns on the wafer. However, with the trend towards scaling down the semiconductor products, the conventional photolithographic technologies face formidable challenges. Take mainstream ArF excimer laser method with wavelength of 193 nm for example, the reachable minimum half-pitch of a transistor device produced by this kind of light source during exposure in the photolithographic process is 65 nm. By incorporating the well-known immersion lithography technology, the reachable half-pitch maybe further reduced to 45 nm, which is almost the physical limitation in the photolithographic processes. For this reason, if the half-pitch of the semiconductor device need to go under 45 nm, the industry needs to utilize more advanced photo-lithographic technologies, such as a double patterning technology, an extreme ultra violet (EUV) technology, a maskless photolithography (ML2) technology or a nano-imprint technology, etc.
Double patterning is one of most mature methods within the aforementioned various advanced photolithography technologies. The double patterning technology enables the use of current available photolithographic tools to produce desired finer circuit patterns, without the requirement of purchasing extremely expensive advanced photolithography tools, thereby avoiding huge investments. As the double patterning technology and relevant equipment gradually mature in the industry, the 193 nm immersion lithography technology once limited by the physical limits can be further applied to the advanced process nodes of 32 nm, or even 22 nm, thereby becoming the mainstream photolithographic technology for the next semiconductor generation.
The principle of the double patterning technology is to separate one compact semiconductor circuit pattern into two alternative or complementary circuit patterns. The two separate patterns will be transferred respectively by the photolithographic process and then be combined on one wafer to obtain the final completed circuit pattern. The use of double patterning technology in nowadays NAND flash processes can produce word lines or bit lines with intervals smaller than 28 nm, thereby significantly improving the memory capacity in memory blocks.
With regard to the application of conventional self-aligned double patterning technology in the manufacture of the NAND flash memory, especially in the manufacture of word lines and select gates in the string area, since the widths of circuit features and/or the intervals therebetween are scaled down to dozens of nanometer, the micro-loading effect resulting from the different densities of the circuit features in the processes may be significantly amplified, so that it is difficult to form the pattern features with good profile characteristics, such as critical dimension uniformity (CDU), line width roughness and line edge roughness, etc., in both the open areas and the dense areas of the circuit pattern. To solve this problem, the common solution in the industry is to dispose additional dummy patterns, ex. dummy word lines, at the boundary between dense regions and open regions, such as the boundary between word line patterns and select gate patterns in a string area. The dummy patterns may serve as a sacrificial structure to replace the non-uniformed circuit features formed by using conventional double patterning method, so that the patterns other than the dummy patterns in the layout may have uniform circuit profiles and characteristics.
In addition to the above-mention approach of dummy patterns, certain process schemes are developed in the industry, which features the use of regular patterns to manufacture circuit pattern with different widths. Please now refer to FIG. 1, which schematically depicting a process scheme for manufacturing a select gate using regular patterns in prior art. As shown in FIG. 1, a poly-silicon layer 12 is formed on a substrate 10 to form word lines and select gates. A plurality of spacers 14 manufactured by double patterning method are formed on the poly-silicon layer 12 to define the pattern of word lines. A flat layer 16 made of planarizable material (ex. an anti-reflective layer) covers the spacers 14 and poly-silicon layer 12. In this process scheme, a photoresist 18 is disposed on the flat layer 16 to define desired select gate region. The photoresist 18 would cover several spacers 14, and preferably, the edges of photoresist 18 are located respectively on the two spacers and do not extend beyond. The select gate and corresponding word lines manufactured by this process scheme would have regular spacing.
However, it is known to those skilled in the art that the photoresist is impossible to be 100 percent precisely located on the predetermined position. To define by the exposure limitation value F of the photolithographic tool, as it can be obviously known from FIG. 1, the photoresist 18 is possible to have an F/2 offset. The F/2 offset maybe half the spacing d between the word lines in current semiconductor technology level, which the dimension of the word line may be configured at several dozens of nanometers. In such severe overlay shift, the spacing of finally-made select gate and adjacent word lines would be severely out of spec and impact the electrical performance of the device. Therefore, it is still urgent to those of skilled in the art to develop or improve the conventional double patterning scheme for the requirement of nano-scale width and density in the semiconductor technology nowadays.